This invention relates to logic circuits and, in particular, to logic circuits for ASIC reliability and yield enhancement.
Application Specific Integrated Circuits (ASIC) typically include gate arrays and standard cells which can be implemented in a plurality of technologies, for example, CMOS, bipolar or BiMOS technology. Gate arrays are typically pre-processed wafers in which familiar standard logic functions can be implemented, for example, an AND function. One advantage of gate arrays is that they provide increased silicon efficiency and consequently higher logic densities and lower costs than previously used large scale integrated circuit design methodologies.
Standard cells comprise various blocks for providing a library of functions ranging form primitive functions such as AND or OR gates to more complex functions such as random access memory (RAM). Typically one designs an standard cell chip by placing and interconnecting blocks wherein each block performs a predetermined function from the library.
As ASIC's grow in size and complexity, it is becoming more important to adequately test an ASIC for reliability and yield. Developing a suitable "test vehicle" to completely test an ASIC for reliability is not an easy task since each individual gate/cell on the ASIC must be tested for functionality. The "test vehicle" becomes even more complex when performing burn-in testing. Burn-in testing is when a sample of ASIC's are powered up for a predetermined period of time and, subsequently tested for reliability and functionality after the predetermined burn-in time. Further, adequate burn-in testing can typically involve repeated testing for a number of predetermined periods. However, the idea behind burn-in testing is that most, if not all, failures will be detected. However, as aforementioned, burn-in testing typically requires one to repeatedly measure the functionality of the ASIC's after a number of predetermined burn-in time periods. This procedure can be quite expensive and even unfeasible.
Hence, a need exists for a novel logic circuit for testing the reliability and yield enhancement for ASIC's.